imec has reported a new sequential CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices., or sCFET, architecture that is meant to scale standard cells while preserving layout efficiency. The approach supports both split-gate and common-gate configurations and is presented as a step toward CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices.-based logic nodes that can continue the classical CMOS1. complementary metal-oxide semiconductorCircuit technology combining n- and p-channel MOS transistors for low static power consumption.2. complementary metal-oxide-semiconductorCMOS is a fundamental semiconductor technology for digital and analog circuits. roadmap into the angstrom era.
The new flow is built around a bonded stack with embedded middle dielectric isolation. The top device is patterned from the front side, then the wafer is flipped and thinned so the bottom device can be defined from the backside. A later via can connect the top and bottom gates when common-gate operation is needed. A second wafer flip completes the process, while the architecture also leaves room for dense backside metal-0 routing.
Compared with monolithic CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. flows, the sequential approach simplifies individual process steps, but it normally requires separate modules for split-gate and gate-connecting use cases. The double-flip sCFET architecture addresses that limitation by offering both options in one structure. In the reported library studies, the architecture reaches an overall efficiency of up to 98%, making it more area-efficient than the double-row and half-height double-row monolithic CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. variants discussed alongside it.
The same split-gate capability also extends CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. scaling to memory. imec presents a 5T+1 CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance. bit cell in which the two single pass-gate transistors are replaced by one CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. transmission gate made from an nFET and a pFET. Because that access device needs independent gate control, the new sCFET split-gate structure is a natural fit. The result is a 5T-like footprint with improved writability compared with a classic 5T SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance..
Beyond logic and SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance., the work also emphasizes improved back-end-of-line routability, which is important for scaling CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. standard cells. The results are tied to imec’s European NanoIC pilot line for beyond-2nm system-on-chip development, where CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices.-specific designs, process steps, modules, and baseline flows are being developed as key enablers for future logic nodes.