The rapid growth of generative and reasoning AIartificial intelligence, together with larger cloud infrastructures, is driving bandwidth demand across data centers and deep into servers. That pressure is exposing the limits of copper interconnects, where low-cost electrical links become power-hungry over longer reaches and at higher lane rates, while signal integrity and thermal constraints worsen.
Optical interconnects are now moving from a data-center solution toward a tighter coupling with the silicon platform. The roadmap described here moves from front-panel pluggable optics, to co-packaged optics, and ultimately to 3D integrated optics inside the wafer stack. Each step shortens electrical paths, improves energy efficiency, and reduces the dependence on heavy digital signal processing for short-reach links.
Pluggable modules remain the dominant architecture for high-speed telecom and datacom. They have scaled from 100G and 200G to 400G and 800G by increasing baud rate, using PAMprocess application moduleSoftware-related method or tool for development, control or data processing.-4 modulation, and expanding lane counts. First-generation 1.6T6 transistor cellA standard SRAM cell with 6 transistors pluggables are now approaching sampling and early deployment, with 200Gbps lanes combined in an eight-lane architecture for DR and FR links over single-mode fiber.
Silicon photonics remains central to that progression. The next step, 3.2T pluggables, will need higher-speed electronics, improved packaging, and better thermal management, plus optical modulators with bandwidths beyond 100GHz. To reach that range, heterogeneous integration is becoming more important, with lithium niobate and lithium tantalate seen as candidates for higher-performance electro-optic devices on SiPho.
Micro-transfer printing has already enabled two notable results: a 320Gbps unamplified O-band link over 2km of single-mode fiber using a 100GHz germanium photodiode and transfer-printed thin-film lithium niobate Mach-Zehnder modulators, and the first heterogeneous integration of a lithium tantalate modulator on a silicon photonic integrated circuit. Both results point to a route for integrating >100GHz electro-optic devices while keeping compatibility with the wafer stack.
For chip-to-chip links inside AIartificial intelligence systems, fast-and-narrow co-packaged optics are becoming the more relevant target. By placing the optical engine adjacent to the ASICapplication-specific integrated circuitIntegrated circuit customized for a specific task, CPOco-packaged opticsOptical devices and CPUs are integrated into a single package reduces the electrical path from centimeters to millimeters, improving signal integrity and latency while avoiding the DSP1. differential signal processingSignal processing based on differences between two signals, often rejecting common interference.2. digital signal processing overhead that becomes costly in short-reach links. imec’s CPOco-packaged opticsOptical devices and CPUs are integrated into a single package targets include optical engines from 1.6T6 transistor cellA standard SRAM cell with 6 transistors and 3.2T toward 6.4T and 12.8T, lane rates of 400Gbps, bandwidth densities near 1Tbps per millimeter, and energy efficiency down to 5pJ/bit and eventually 3pJ/bit.
The more advanced OIO2.5D and OIO3D concepts push integration further. OIO2.5D combines photonic and electronic dies on a shared silicon interposer and targets 8-32Tbps optical engines, 32-64Gbps per-lane operation, and wavelength-division multiplexing with 8-32 wavelengths per fiber. OIO3D moves photonic layers into the wafer stack itself, aiming for tens of terabits per second, sub-pJ/bit operation in the long term, and ultra-short electrical paths at micrometer scale.
The work also extends to materials and package integration. A beyond-110GHz GeSi electro-absorption modulator has already demonstrated sustained net-400Gbps per lane, and a 300mm-compatible process for integrating barium titanate on silicon photonics has been announced with molecular beam epitaxy on large wafers. Together, these results define a roadmap in which optical interconnects are being scaled by combining higher-speed devices, denser packaging, and heterogeneous materials integration.