S2C used the sixth RISC-Vreduced instruction set computer fiveRISC-V is an open instruction set architecture used for processor design. Summit China to present a development flow aimed at shortening RISC-Vreduced instruction set computer fiveRISC-V is an open instruction set architecture used for processor design. bring-up before first silicon. The company connected three steps in that flow: executing sizable RISC-Vreduced instruction set computer fiveRISC-V is an open instruction set architecture used for processor design. systems on FPGAfield-programmable gate arrayReconfigurable logic device whose internal circuits can be programmed after manufacturing. hardware, automating the first compilation analysis for RTL1. resistor-transistor logicSemiconductor device or transistor technology used to control electrical currents and signals.2. register transfer levelRTL is the hardware description layer where design assumptions are often captured.3. Register-Transfer LevelRTL describes the hardware implementation stage targeted by the benchmark., and applying large language models to debug data from a virtual platform.
One booth demonstration paired an Andes Technology AX66-based RISC-Vreduced instruction set computer fiveRISC-V is an open instruction set architecture used for processor design. configuration with Linux KVM on S2C’s Prodigy S8-100 FPGAfield-programmable gate arrayReconfigurable logic device whose internal circuits can be programmed after manufacturing. prototyping system. The design consumed 55% of the resources on a single AMD Versal Premium VP1902 FPGAfield-programmable gate arrayReconfigurable logic device whose internal circuits can be programmed after manufacturing., a figure that underlines the available headroom for multicore, 64-bit RISC-Vreduced instruction set computer fiveRISC-V is an open instruction set architecture used for processor design. IP1. image placement2. Internet protocolInterface or communications concept for transmitting data between devices and systems.3. Intellectual PropertyIP denotes licensable semiconductor design blocks or technology elements. prototyping rather than final-silicon benchmarking.
S2C framed that capacity around early software validation, including edge AIartificial intelligence inference workloads. The Linux KVM layer adds operating-system interactions to the pre-silicon environment, allowing software behavior to be exercised before manufactured chips are available. The setup was presented as a prototyping and validation platform, not as a measurement of final chip performance or application throughput.
The company also showed RCF Agent using RTL1. resistor-transistor logicSemiconductor device or transistor technology used to control electrical currents and signals.2. register transfer levelRTL is the hardware description layer where design assumptions are often captured.3. Register-Transfer LevelRTL describes the hardware implementation stage targeted by the benchmark. from the open-source XiangShan RISC-Vreduced instruction set computer fiveRISC-V is an open instruction set architecture used for processor design. processor. In that flow, the agent starts compilation, collects error messages, and generates an initial analysis. The aim is to automate repetitive preparation work that usually comes before a large design can be developed further.
That first-pass analysis matters because teams must get a working compilation flow and understand failures before deeper functional debugging can begin. The demonstration focused on initial triage; it did not claim that the agent resolves every error on its own or replaces engineering review.
In the summit’s chip design and verification forum, S2C also presented an LLM1. local linear models2. Large Language ModelThe model class referenced in the long-context serving demo.-based RISC-Vreduced instruction set computer fiveRISC-V is an open instruction set architecture used for processor design. virtual-platform and debug flow. The modeled environment covers the processor, memory, buses, an interrupt controller, and common peripherals, and can boot firmware, bootloaders, and operating systems while supporting breakpoints, watchpoints, state inspection, and execution tracing.
Saving and restoring execution state was presented as a key feature for collaborative debugging, because it creates a repeatable starting point for comparing outcomes and sharing failures across teams. The LLM1. local linear models2. Large Language ModelThe model class referenced in the long-context serving demo. layer is intended to help organize and interpret captured debug information, while engineers remain responsible for validating conclusions against the underlying execution data.