Test strategies for AIartificial intelligenceAI stands for artificial intelligence and data center silicon are shifting toward using the device interfaces already present on the chip. As logic count, core count, and scan content increase, more data has to reach the device for test, and chiplet-based packages add another layer of complexity because each die brings its own test requirements and patterns.
Siemens’ Tessent Streaming Scan Network addresses that problem by packetizing scan data so it can be delivered more efficiently and shared across cores. Tessent In-System Test extends the approach with an on-chip controller that accepts deterministic patterns over a standard AXIAdvanced eXtensible InterfaceAXI is an AMBA interface used widely for high-performance on-chip data movement. bus, allowing test content to arrive through a functional interface such as PCIePeripheral Component Interconnect ExpressPCIe is the high-speed serial interconnect standard or USBUniversal Serial BusUSB is a standard interface for peripheral connectivity and data transfer. instead of a dedicated test port.
The same flow has been tied to Teradyne’s UltraFLEXplus. Teradyne has integrated Siemens Tessent Silicon Executable into the UltraPort server and the IGintrinsic getteringTrapping metal impurities at internal defect sites within a silicon wafer.-XL software on UltraFLEXplus, so content generated in the Tessent shell flow can be delivered over the device’s PCIePeripheral Component Interconnect ExpressPCIe is the high-speed serial interconnect standard interface through UltraPort. Test setup, execution, and debug then stay inside the standard IGintrinsic getteringTrapping metal impurities at internal defect sites within a silicon wafer.-XL programming model.
Failure data returns in the formats the Tessent diagnosis ecosystem already consumes, which keeps established yield and failure analysis flows usable. The combined approach is positioned as a single solution spanning embedded software, hardware, and integration rather than a chain of separate tools.
The broader context is a test environment that has changed with AIartificial intelligenceAI stands for artificial intelligence buildouts. Devices are larger, draw more power, and are increasingly built from chiplets, where a weak die can compromise a package worth much more than the die itself. That pushes more of the test-cost decision earlier into the design flow, where DFT1. design for testabilityDesign approach that makes circuits easier to test after manufacturing.2. design for testInclusion of test structures and design rules to make integrated circuits easier to test. architecture is defined before a device ever reaches a tester.
In that setting, the alignment between design and test matters more than ever. The workflow described here keeps scan content moving over a high-bandwidth interface the device already carries, keeps bring-up and debug in the same flow that generated the patterns, and preserves the DFT1. design for testabilityDesign approach that makes circuits easier to test after manufacturing.2. design for testInclusion of test structures and design rules to make integrated circuits easier to test. work from design through production, bench use, and in-system test.