Speakers at iTechCon 2026 argued that AIartificial intelligence system design is moving decisively beyond chip-centric optimization. As workloads shift from training toward inference, agentic AIartificial intelligence, and physical AIartificial intelligence, the relevant design problem increasingly spans chips, models, software, and the surrounding system architecture.
The panel, held during the 2026 EE Tech Summit in Taiwan, focused on how the island’s semiconductor manufacturing, advanced packaging, and system integration strengths can be translated into higher-value AIartificial intelligence system development. Participants also pointed to gaps in software expertise, cross-disciplinary talent, and startup formation that still need to be addressed.
AMD’s David Wang said agentic AIartificial intelligence depends on both GPUgraphics processing unitA GPU is a parallel graphics processor widely used for AI acceleration.s and CPUcentral processing unitMain processor that executes program instructions and performs data operations.s, with CPUcentral processing unitMain processor that executes program instructions and performs data operations.s handling task execution, tool orchestration, and workflow management. He also stressed that future AIartificial intelligence systems will rely on heterogeneous computing, combining CPUcentral processing unitMain processor that executes program instructions and performs data operations.s, GPUgraphics processing unitA GPU is a parallel graphics processor widely used for AI acceleration.s, NPUNeural Processing UnitA processor optimized for neural-network inference workloads.s, and dedicated accelerators according to workload requirements. For edge devices, robots, and industrial equipment, power efficiency, low latency, and real-time responsiveness become central design constraints.
Yung-Hui Li of Hon Hai Research Institute described AIartificial intelligence system design as expanding from single chips to racks and even data centers, where compute, memory, interconnects, networking, power delivery, liquid cooling, and software must be co-optimized. He noted that bottlenecks are increasingly appearing in data movement, power delivery, and thermal management, not just raw compute throughput.
That shift is also changing the metrics used to judge systems. Li said performance per watt and tokens generated per dollar are becoming more relevant than FLOPSfloating-point operations per secondA traditional metric to describe the computing power alone. In that context, chips, memory, interconnects, and cooling all have to be designed together to improve overall system efficiency.
The discussion also emphasized Taiwan’s broader industrial ecosystem, including semiconductors, advanced packaging, PCBprinted circuit boardBoard that mechanically supports components and electrically interconnects them with copper traces.s, power delivery, thermal management, networking, and servers. Li said the combination of manufacturing depth and tight industry integration helps Taiwan move quickly from design validation to mass production. Taiwan’s Industrial Development Administration added that existing supply chains and international partnerships would be difficult to replicate quickly elsewhere.
Neuchips founder Yung-Long Lin argued that AIartificial intelligence chips alone cannot create a durable advantage. Models, software, circuits, and chip architectures must be optimized in parallel, and co-design has to start early rather than after hardware handoff. Li added that low-precision computing and sparsity only help if models, compilers, and runtime environments are designed to exploit them.
The panel also pointed to physical AIartificial intelligence as a particularly demanding case, because robots and smart devices must process multimodal sensor inputs in real time under tight power and thermal budgets. Safety, reliability, verification, and redundancy were described as essential, especially when control loops must respond within milliseconds and cannot depend on round-trip network communication.
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