Embedded memory, rather than compute, is now the dominant constraint in many AIartificial intelligence and HPC1. High Performance ComputingCompute applications with particularly high performance demands, cited here as a driver for packaging and testing.2. high-performance computingHPC denotes compute-intensive chips that require advanced testing support. SoCs. The pressure comes from area consumption as well as from bandwidth, latency, and energy-efficiency limits, with embedded memory taking more than half of total die area in these designs.
The technical shift matters because the industry is moving to gate-all-around devices and backside power delivery networks. In that environment, embedded memory architectures need to evolve alongside the logic process, instead of remaining a fixed IP1. image placement2. Internet protocolInterface or communications concept for transmitting data between devices and systems.3. Intellectual PropertyIP denotes licensable semiconductor design blocks or technology elements. block optimized for older integration assumptions.
Synopsys has positioned its Embedded Memory IP1. image placement2. Internet protocolInterface or communications concept for transmitting data between devices and systems.3. Intellectual PropertyIP denotes licensable semiconductor design blocks or technology elements. around that transition. The approach combines device-aware architectures, power-optimized designs, and highly configurable compilers to better fit advanced-node requirements. The stated goal is to reduce the integration friction that appears when memory, power delivery, and transistor architecture all change at once.
Silicon data from SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance. and Register File test chips on Intel 18A provide the concrete benchmark. Those results show density improvements in the 5% to 10% range, along with ISO-power performance gains of up to approximately 4%. The measurements indicate that the memory IP1. image placement2. Internet protocolInterface or communications concept for transmitting data between devices and systems.3. Intellectual PropertyIP denotes licensable semiconductor design blocks or technology elements. can deliver measurable gains rather than only architectural promises.
The material also ties those gains directly to RibbonFET and PowerVia. By aligning embedded memory with gate-all-around transistors and backside power delivery, the design is intended to improve PPA1. power, performance, and areaPPA is the main optimization target for advanced-node designs.2. power, performance, area while lowering advanced-node integration risk.
For AIartificial intelligence and HPC1. High Performance ComputingCompute applications with particularly high performance demands, cited here as a driver for packaging and testing.2. high-performance computingHPC denotes compute-intensive chips that require advanced testing support. SoCs, the message is straightforward: memory is no longer a passive companion to compute. It has become a primary scaling constraint, and the available silicon results suggest that process-aware memory IP1. image placement2. Internet protocolInterface or communications concept for transmitting data between devices and systems.3. Intellectual PropertyIP denotes licensable semiconductor design blocks or technology elements. can recover some area and power headroom at Intel 18A.
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