Imec has completed the baseline flows for its silicon interposer platform in the NanoIC pilot line, marking an early technical milestone for chiplet integration in Europe. The work is intended to form the basis of a dedicated process design kit and, later, low-volume prototyping options for advanced packaging.
The silicon interposer is one of three interconnect technologies under development in NanoIC, alongside fine-pitch RDLRedistribution LayerRDL patterning is a key step in advanced packaging for rerouting chip I/O. interposers and die-to-wafer hybrid bonding. Together, these platforms are being translated into dedicated PDKprocess design kitA PDK provides the technology files and design rules needed to design chips for a specific process.s so that universities, start-ups and fabless companies can evaluate chiplet-based system concepts before manufacturing starts.
Silicon interposers act as a high-density routing layer beneath the dies in a package. They are positioned to link compute chiplets, high-bandwidth memory and other specialized dies with short, dense interconnects, which is especially relevant for AIartificial intelligenceAI stands for artificial intelligence accelerators, GPUgraphics processing unitA GPU is a parallel graphics processor widely used for AI acceleration.s and other multi-die systems where bandwidth and energy-efficient data movement are key requirements.
The reference platform captures the architecture, manufacturing flow and main design characteristics of the technology. It includes through-silicon vias, multiple metal routing layers and support for microbump pitches down to 20 µm, enabling the density needed for 2.5D packages that combine chiplets, memory and other dies.
The dedicated silicon interposer PDKprocess design kitA PDK provides the technology files and design rules needed to design chips for a specific process. is scheduled for release in early 2027. It will be usable in standard EDA1. electronic design automationSoftware tools for designing, simulating, verifying and laying out electronic circuits.2. equipment data acquisitionSystem or method for collecting, storing, exchanging or analyzing data. environments from Cadence and Synopsys, giving users a way to explore the technology virtually and assess heterogeneous system architectures. The interposer PDKprocess design kitA PDK provides the technology files and design rules needed to design chips for a specific process. will complement existing NanoIC interconnect PDKprocess design kitA PDK provides the technology files and design rules needed to design chips for a specific process.s for fine-pitch RDLRedistribution LayerRDL patterning is a key step in advanced packaging for rerouting chip I/O. interposers and die-to-wafer hybrid bonding.
Longer term, NanoIC plans to extend this virtual access into physical silicon demonstrators on the pilot line. The program is supported by the Chips Joint Undertaking through the European Union’s Digital Europe and Horizon Europe programs, together with Belgium (Flanders), France, Germany, Finland, Ireland and Romania.