Manufacturers scaling advanced AIartificial intelligenceAI stands for artificial intelligence packages are under pressure to move from process development to high-volume manufacturing faster while protecting yield. That pressure is particularly visible in fan-out panel-level packaging, where larger panels promise better substrate utilization and more packages per substrate, but also introduce difficult lithography control problems.
One comparison highlights the economic case for the format: a 300 mm wafer reached about 55 % substrate utilization with six packages per wafer, while a 300 mm panel achieved 86 % utilization with 12 packages per panel. A 510 × 515 mm panel reached 74 % utilization with 30 packages per panel. The higher package count per substrate can lower cost, but only if the process window can be stabilized quickly.
The lithography challenge comes from panel-scale variation. As panel sizes grow, pattern distortion, die shift, and overlay errors become more pronounced and less uniform across the substrate. That makes conventional correction methods harder to tune because the distortion pattern may change from area to area rather than follow a consistent wafer-scale behavior.
Several correction strategies are used to balance yield against throughput. Global correction preserves throughput but can leave local overlay errors unresolved. Zone correction can improve yield, with field data in the study showing values between 40 % and 80 %, but at a throughput penalty. Die-by-die correction can push yield further while slowing production more strongly. Site-by-site correction sits between those extremes.
The difficult part is finding the operating point that gives acceptable overlay yield without sacrificing too much throughput. That usually requires repeated experiments across exposure field configuration, die layout, panel layout, and overlay thresholds. Each change can trigger another trial run and another analysis cycle, increasing engineering effort, material use, and time to ramp.
Yield prediction is presented as a way to reduce that trial-and-error loop. By combining offline metrology data with yield prediction algorithms, engineers can estimate likely yield outcomes before running extensive physical trials. The workflow uses detailed measurements of panel-scale variation, including pattern errors and die shifts, together with process variables such as exposure field configuration, panel layout, die layout, and overlay thresholds.
The output is not limited to a single prediction number. Heat maps, vector plots, histograms, and yield dashboards help reveal sensitivities and isolate root causes more quickly. In one example, comparison of error maps showed that the Y-axis carried the larger overlay error contribution and therefore the main yield loss mechanism.
In HVMhigh volume manufacturing testing, predicted and measured yield initially differed by 1.2 % to 2.7 %. The mismatch was traced mainly to variability in manual inspection judgment. After inspection was standardized, prediction error dropped to 0.2 % to 0.8 %, showing that the method can become more precise when measurement practice is controlled.
The same approach is also being used earlier in development, where simulated evaluation of process conditions can help narrow the number of qualification runs needed. In mass production, the concept extends into real-time, in-line monitoring inside the lithography workflow, with the goal of catching defects earlier and reducing rework, manpower, time, and cost.
For FOPLP, the practical message is that lithography ramp speed is increasingly tied to learning-cycle length. Yield prediction is being used to compress that learning phase, support faster process refinement, and move panel-level packaging toward stable, high-yield production with fewer physical iterations.