A joint research effort involving UC Berkeley, Samsung Electronics, and Intel has introduced a nanoelectromechanically gated gain cell for embedded DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology. The work is positioned as a response to the “memory wall” and to the slowdown in SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance. scaling, both of which have renewed interest in gain-cell memory for on-chip storage.
Gain cells remain attractive because they can deliver higher density and better energy efficiency than SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance., but their practical use has been constrained by three recurring issues: limited data retention, parasitic coupling, and the need for boosted write voltages. The new device concept is designed specifically around those limitations rather than around incremental tuning of conventional gain-cell structures.
The reported architecture uses a nanoelectromechanical gate to control the gain cell in the eDRAM configuration. That gating mechanism is intended to preserve the compact, low-power advantages of gain cells while changing the way the storage element is accessed and written. The paper presents this as a route toward more efficient embedded memory, rather than as a general-purpose replacement for DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology or SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance..
The publication, “Nanoelectromechanically Gated Gain Cell eDRAM,” appears in the IEEEInstitute of Electrical and Electronics Engineers Journal on Exploratory Solid-State Computational Devices and Circuits and is listed as an open-access paper from October 2026. The article is authored by Finnan, Collin P., Choong-Ho Rhee, Tahir Ghani, and Tsu-Jae King-Liu.
Beyond the headline concept, no additional device metrics, endurance figures, or process integration details are provided in the available material. The main technical point is the combination of nanoelectromechanical gating with gain-cell eDRAM to attack the retention and write-voltage weaknesses that have limited the format’s adoption.
In practical terms, the work adds a new device-level option to the search for denser and lower-power embedded memories as SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance. scaling loses momentum. The contribution is not a finished product announcement, but a published circuit and device concept aimed at improving the efficiency of on-chip DRAM1. dynamic random access memoryMemory technology or system for temporarily or permanently storing digital information.2. dynamic random-access memoryDRAM is a volatile memory technology storage.