Conventional gate-all-around nanosheet transistors are approaching scaling limits tied to leakage, mobility, resistance, and manufacturing variability. A self-aligned complementary field-effect transistor, or SA-CFETself-aligned complementary field-effect transistorA CFET architecture that uses self-aligned integration modules., is positioned as an alternative architecture for continuing CMOS1. complementary metal-oxide semiconductorCircuit technology combining n- and p-channel MOS transistors for low static power consumption.2. complementary metal-oxide-semiconductorCMOS is a fundamental semiconductor technology for digital and analog circuits. scaling beyond the 10 Å node.
The core idea is to stack NMOS1. negative channel metal-oxide semiconductor2. n-channel metal-oxide-semiconductorThe n-channel device type used in the stacked CFET structure. and PMOS1. positive channel metal-oxide semiconductor2. p-channel metal-oxide-semiconductorThe p-channel device type used in the stacked CFET structure. devices vertically rather than place them side by side. That arrangement can reduce cell area, increase effective channel width, and improve electrostatic control. The proposed flow uses self-aligned modules to make the integration more manufacturable at very small dimensions.
Three process modules form the backbone of the concept: SA-BPRself-aligned buried power railA self-aligned module used to route buried power rails. for buried power rails, SA-CTself-aligned contactsA self-aligned module used to form contacts. for contacts, and SA-TSVself-aligned through-silicon viaA self-aligned module used for vertical interconnects through silicon. for through-silicon vias. Together they are intended to widen the edge placement error window and reduce contact crowding, while turning overlay-sensitive steps into self-aligned ones. The architecture also uses a non-metal gate cut and middle dielectric isolation for work-function split.
The design remains compatible with N33-nanometer nodeA reference technology node used for area comparison.-style specifications, including a 42-nm contacted poly pitch and a 21-nm metal pitch. Within that framework, the process sequence supports both 6T6 transistor cellA standard SRAM cell with 6 transistors SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance. cells and standard logic cells such as NOT, NANDNot ANDA logic gate that outputs 0 when all inputs are 1, and outputs 1 in all other cases, and NOR, without requiring a metal gate split within any single fin.
Digital twin process modeling with SEMulator3D was used to validate the integration flow and the interconnection network. The results show a 6T6 transistor cellA standard SRAM cell with 6 transistors SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance. bit cell area of 0.0094 µm², which is 52.7% smaller than N33-nanometer nodeA reference technology node used for area comparison. technology and 19% smaller than a state-of-the-art A7A7 technology nodeA CFET design node used for the area comparison. CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. design.
Process robustness also appears strong. The validation reported at least a 10-nm overlay window across all critical contact layers, with no open or short failures. That margin is central to the pitch of the proposal, because CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. integration faces growing risks from metal gate isolation complexity and contact crowding as dimensions shrink further.
Overall, the work presents a self-aligned CFETcomplementary field-effect transistorA transistor architecture that vertically stacks NMOS and PMOS devices. process sequence for SRAM1. static random access memoryMemory technology or system for temporarily or permanently storing digital information.2. static random-access memorySRAM is used here as a test vehicle for embedded memory performance. and logic that aims to preserve manufacturability while avoiding several of the scaling issues that increasingly affect nanosheet transistors at and beyond the 10 Å node.