Short updates from the semiconductor industry, with context and links to the relevant chapters. RSS
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October 29, 2026 Design & EDA
As semiconductor designs grow larger and regressions produce more simultaneous failures, debugging is turning into an orchestration problem. An AI-native workflow combines intelligent binning, witness simulation reruns, autonomous root cause analysis, and verification to reduce the number of failures that need separate investigation and to spend compute only where it is most useful.
October 29, 2026 Design & EDA
Semiconductor design agents are only reliable when every autonomous step is checked against deterministic physics-based EDA engines. Siemens describes a multi-stage electro-thermal 3D-IC workflow in which validation happens continuously, not only at the end of a run.
October 25, 2026 Design & EDA
Researchers at the Technical University of Munich have developed neural network transistor models for ultra-fast SPICE simulation and standard cell library characterization. The models predict drain current and multiple charge components for a 3 nm nanosheet device, then run through standard-cell characterization and additional analog and digital circuit simulations against an industry-standard reference model. In the reported tests, the neural networks produced delay and total-power estimates with sub-0.11% and 0.76% error, while cutting characterization time by up to 8x.
October 19, 2026 Design & EDA
Calibre DesignEnhancer Via automates the insertion of additional vias to improve resistance, electromigration margin and routing density in physical design. The flow also avoids short-prone regions, aiming to keep layouts DRC-clean while reducing late signoff iteration.
September 29, 2026 Design & EDA
Siemens and TSMC are broadening their collaboration on design tools with an emphasis on AI-assisted workflows, advanced packaging, and support for newer manufacturing processes. The announcement highlights an AI agent meant to identify and correct design rule violations before they block a layout from moving forward.
September 29, 2026 Design & EDA
As more computing power is concentrated in a single system, the bottleneck is shifting from individual die performance to the complexity of connecting multiple chips, memory stacks, power delivery, and sometimes optical components inside one compact package.
September 24, 2026 Design & EDA
AI is moving deeper into EDA, but the article argues that speed alone is not enough. Trust in automated design flows will depend on formal proof, semantic continuity across tools, and auditable handoffs that preserve design intent from one stage to the next.
September 24, 2026 Design & EDA
Multi-chiplet heterogeneous integration is pushing design data, IP traceability, and revision control into the critical path. Semiconductor Engineering argues that without a single source of truth, wrong versions, missed ECOs, and overwrites can quickly turn into delays or even product failure.
September 19, 2026 Design & EDA
NYU researchers report an offline reinforcement-learning approach that uses an LSTM-based policy to lower persistent rule violations during detailed routing in dense physical designs.
September 19, 2026 Design & EDA
Researchers at Purdue University have introduced DRC-Aid, a closed-loop agentic framework that repairs local design-rule violations with an inference-time large language model while preserving layout equivalence. The system turns verification output into a bounded set of geometric edits and searches for fixes inside that constrained space.
September 15, 2026 Design & EDA
Rising power density and chiplet complexity are pushing thermal management into earlier design stages, with engineers now balancing chip, package, board, and system effects in a single multi-physics flow.
September 15, 2026 Design & EDA
AI is starting to assist both hardware and software development, but integrated co-design still runs into organizational silos, mismatched tools, and the lack of models that are fast enough and accurate enough for continuous iteration.
September 15, 2026 Design & EDA
Operating a SoC near or below MOSFET threshold voltage changes the design rules. The article outlines why standard low-power libraries, coarse corner models, and ordinary test flows are not enough in the ultra-low-voltage regime.
September 14, 2026 Design & EDA
OpenAI has presented Jalapeño, its first in-house AI accelerator, and says internal LLMs helped compress the design cycle dramatically. The chip combines a compute die with six stacks of HBM4 and an I/O chiplet.
September 1, 2026 Design & EDA
Hardware-assisted verification is moving beyond expensive emulator setups as FPGA-based prototyping gives teams a faster way to validate complex SoC hardware and software together before silicon is available.