Short updates from the semiconductor industry, with context and links to the relevant chapters. RSS
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September 30, 2026 Research
China’s 3D DRAM effort is shifting beyond lab work, with IMECAS, SAMT, CXMT and NAURA Technology Group all involved in the move toward wafer processes and equipment. The development signals progress from early research, but mass production still faces major technical hurdles.
September 30, 2026 Industry & People
At A*STAR’s Innovate Together 2026, industry specialists discussed how AI is reshaping packaging requirements, from hybrid bonding and optical interconnects to tighter process control.
September 30, 2026 Industry & People
Global Foundry 2.0 market revenue climbed to a record $96.6 billion in the second quarter of 2026, driven by data-center expansion and stronger demand across networking, power management, mature-node chips, packaging, and test.
September 30, 2026 Supply Chain & Sites
India’s push to build a domestic chip ecosystem is already pulling the materials supply chain onshore. As Tata Electronics advances its Dholera fab and packaging projects take shape in Sanand, suppliers of industrial gases, wet chemicals and photoresists are positioning themselves near future customers in Gujarat.
September 30, 2026 Industry & People
HBM is becoming a major cost driver in GPU-based CoWoS packaging, raising the question of whether memory can still be treated as a passive part of AI computing. The discussion ties back to the long-running memory wall that has influenced semiconductor development for decades.
October 1, 2026 Companies & Market
Applied Materials and Besi are widening their joint development work on advanced packaging by bringing Besi into Applied’s EPIC Center as an Innovation Partner. The collaboration now reaches beyond hybrid bonding into next-generation interconnect architectures, 3D IC scaling, logic and memory integration, and photonics-oriented applications.
October 1, 2026 Companies & Market
Renesas Electronics has introduced a dual-side-cooled 650-V GaN device for high-voltage power conversion in AI data centers. The new package spreads heat from both the top and bottom, cuts footprint by 57% versus the prior TOLT option, and targets 800-V intermediate bus converters in space- and thermally constrained racks.
October 2, 2026 Research
A free webinar will examine how full-wave finite-element simulation and semianalytical multipole decomposition in COMSOL Multiphysics can be used to design dielectric metasurfaces that control transmission, reflection, and absorption. The focus is on silicon and gallium nitride structures, where different multipole mechanisms are arranged to produce anomalous absorption enhancement and q-BIC-related spectral shaping.
October 5, 2026 Research
Researchers from Syracuse University, Friedrich-Alexander-Universität Erlangen-Nürnberg, and TU Dresden have introduced RAPID, a row-parallel arithmetic processing-in-DRAM architecture. The approach adds migration cells for local horizontal movement between neighboring bitlines and inversion cells for in-array logical inversion, allowing DRAM to work on row-parallel, bit-parallel data instead of forcing column-oriented, bit-serial reorganization.
October 5, 2026 Research
Researchers at the University of California, Santa Cruz have explored backside clock meshes for 2 nm GAAFET BSPDN technology. The approach uses the backside metal stack to reduce clock skew and save routing resources on premium frontside layers, while still relying on through-silicon vias to reach flip-flops on the frontside.
October 5, 2026 Research
Researchers from HUST, Hong Kong Polytechnic University, UC Santa Barbara, and the National University of Singapore report ballistic p-type WSe2 monolayer transistors with lower contact resistance and higher on-state current. The work targets one of the main bottlenecks for extending 2D semiconductors toward sub-1-nm CMOS circuits.
October 6, 2026 Research
A new technical roundup highlights work on low-contact-resistance WSe₂ transistors, backside clock meshes for 2nm GAAFETs, row-parallel DRAM processing, HBF for high-throughput LLM serving, formal CAN XL security analysis, and methods for abstraction and validation from physical devices to RTL.
October 6, 2026 Companies & Market
Applied Materials and Intel are deepening their collaboration on next-generation transistors, interconnects and advanced packaging for AI computing. The work combines Applied’s EPIC Center in Silicon Valley with Intel’s R&D campus in Hillsboro, with the stated goal of shortening the path from lab-scale development to high-volume manufacturing.
October 6, 2026 Research
Researchers from Seoul National University and Yonsei University have demonstrated a monolithically integrated memristor-thin-film transistor kernel for multimode reservoir computing. By vertically combining Ru/HfO2/TiN memristors with In2O3 channel TFTs, the structure allows the temporal conductance dynamics to be tuned electrically across a broad time scale.
October 6, 2026 Research
Researchers from ETH Zürich, CISPA, and New York University have proposed Terracotta, a framework that pairs custom DRAM command extensions with a programmable memory controller. The approach is designed to reduce the repeated redesign effort that has slowed the deployment of techniques for in-DRAM computation, lower latency, higher parallelism, and improved maintenance and reliability.