Short updates from the semiconductor industry, with context and links to the relevant chapters. RSS
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September 19, 2026 Design & EDA
NYU researchers report an offline reinforcement-learning approach that uses an LSTM-based policy to lower persistent rule violations during detailed routing in dense physical designs.
September 19, 2026 Research
Researchers at the University of Michigan have introduced Fengshui, a co-design framework that jointly optimizes chiplet ecosystem composition and bespoke neural-network accelerator design. The work targets lower energy use and reduced design cost by treating the chiplet pool and the accelerator architecture as one problem.
September 19, 2026 Research
Researchers from the University of Technology Sydney, ShanghaiTech University, and the Technical University of Munich have introduced IC-ThermBench, an open benchmark for evaluating machine-learning models that predict temperature in advanced package architectures. The dataset combines established 3D-IC tasks with a new 50,000-sample 2.5D chiplet extension.
September 19, 2026 Research
Researchers at Heidelberg University have presented a unified interconnection network for chiplet-based scaling of the BrainScaleS-2 neuromorphic system. The design addresses two traffic classes: error-tolerant spike communication and error-intolerant data such as configuration traffic and exchanges between processing units.
September 20, 2026 Industry & People
Listed Taiwanese equipment, component, and solutions suppliers are expanding at nearly twice the pace of the chipmakers they serve, with test emerging as the main driver. The strongest momentum comes from production steps tied to AI accelerators.
September 21, 2026 Companies & Market
China’s two major memory makers, CXMT and YMTC, are reportedly moving into each other’s core product areas as they seek to benefit from AI-driven demand for memory chips.
September 21, 2026 Artificial intelligence
Vision-language-action models can look impressive in the lab, but moving from a demo to broad deployment requires more than faster chips. The gap lies in making robotic systems robust, repeatable, and practical beyond controlled test setups.
September 21, 2026 Devices & Products
EDN’s teardown of TP-Link’s TL-SM311LS examines a long-range fiber module marketed as an LX “Mini GBIC Module”. The inspection identifies the optical receiver and laser transmitter, along with an EEPROM from Giantec Semiconductor and a G/EPON ONU transceiver from Xiamen UX High-Speed IC.
September 21, 2026 Devices & Products
A 60 GHz FMCW radar front end can keep track of occupancy and motion while leaving the host MCU, camera, or other higher-power blocks asleep. Infineon’s XENSIV BGT60CUTR13AIP is used as an example of how antenna-in-package integration and on-chip processing reduce standby power in battery-powered IoT designs.
September 21, 2026 Research
SK Hynix is developing a next-generation 3D DRAM architecture that splits the memory-cell array from the peripheral control circuits, so each block can be built with a process optimized for its role. The approach also requires significantly more logic-design expertise than conventional DRAM development.
September 21, 2026 Research
At ECOC 2026, imec reported a Ge/Si avalanche photodiode on its 300 mm silicon photonics platform that combines 100 GHz bandwidth, 5 V operation and 1.8 A/W responsivity, and was used to demonstrate the first net 400 Gbps optical link with an APD receiver.
September 22, 2026 Research
A technical paper from the University of Minnesota outlines design methods for delivering very high power in advanced 3D heterogeneous integration, where pin-count limits and power density make robust supply delivery increasingly difficult.
September 22, 2026 Manufacturing & Processes
As AI accelerators and HPC processors scale to more cores, chiplets, and scan elements, Synopsys is pairing unified test compression with a programmable streaming fabric to move test data more efficiently across large hierarchical designs.
September 22, 2026 Devices & Products
Infineon’s PSoC Control C3 Performance Line combines dual-core Arm Cortex-M33 operation at up to 200 MHz with a programmable power control accelerator, WBG readiness, and post-quantum cryptography for secure firmware handling in demanding power and motor applications.
September 22, 2026 Devices & Products
Space-qualified analog ICs are no longer limited to expensive, order-to-build programs. Vendors are increasingly listing basic analog functions such as current sensing, buffering, and temperature measurement as standard catalog items, reducing schedule risk and cost for satellite designers.