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August 29, 2026 Research

PPAPlace predicts post-route PPA during chip placement

Researchers at the University of Alberta introduced PPAPlace, a placement-time surrogate that estimates post-route timing, power, and area from macro and standard-cell locations. The method replaces wirelength-only optimization with differentiable cross-stage objectives trained on post-global-routing labels.

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August 28, 2026 Research

Deep learning automates parameter extraction for 2D transistors

Researchers at Stanford University and SLAC National Accelerator Laboratory have shown a neural-network approach that extracts physical parameters of 2D transistors directly from electrical measurements. The method targets mobility, Schottky contact barrier height, and defect profiles, and it is designed to speed up both automated parameter extraction and TCAD model fitting.

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