News – Page 16 - Halbleiter.org

October 27, 2026 Companies & Market

S2C pushes faster RISC-V bring-up with FPGA prototyping and AI-assisted debug

At the sixth RISC-V Summit China, S2C highlighted a three-part workflow for earlier processor validation: FPGA prototyping for substantial RISC-V systems, automated first-pass RTL compilation analysis, and LLM-assisted interpretation of virtual-platform debug data. The demonstrations centered on an Andes Technology AX66-based RISC-V configuration running Linux KVM on S2C’s Prodigy S8-100 system, plus tooling around XiangShan RTL and a virtual platform for reproducible debug.

Infineon launches LinearFET for automotive solid-state power distribution

Infineon has introduced LinearFET, a MOSFET technology aimed at simplifying next-generation solid-state power distribution in electric and software-defined vehicles. The device-level approach integrates current sharing, inrush current control, and short-circuit robustness to reduce external circuitry, board space, and implementation complexity.

Infineon launches ENDOPACK chip-embedding platform for high-voltage traction inverters

Infineon has introduced ENDOPACK, a new chip-embedding platform that extends PCB-based integration from low-voltage production into high-voltage power electronics. The first product, ENDOPACK Cell, is an automotive-qualified 1200 V solution with CoolSiC MOSFETs built directly into the board, targeting faster traction-inverter development, higher design flexibility, and lower inductance than conventional module approaches.

Infineon and Enphase extend GaN bidirectional switches to 900 V for SST power modules

Infineon will supply Enphase Energy with the first 900 V gallium nitride monolithic bidirectional switches for solid-state transformer power modules. The devices are aimed at AI data centers and are intended to combine higher voltage headroom with the high-frequency switching needed for compact, efficient power conversion.

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October 27, 2026 Companies & Market

Infineon introduces 5.6 kW M-CRPS reference design for dense enterprise AI servers

Infineon has launched a 5.6 kW modular common redundant power supply reference design for enterprise servers and edge AI systems. The compact 185 mm M-CRPS platform combines a peak efficiency above 98%, 170 W/in³ power density, and a 54 VDC output with fast transient response for AI workloads.

Intel Foundry Links Metrology, AI, and Packaging Data for More Connected Manufacturing

Intel Foundry is framing manufacturing autonomy as a measurement problem first: without trustworthy metrology, connected data, and human oversight, AI cannot safely improve fab decisions. The company’s SEMICON West 2026 presentations point to work across defect classification, thermal modeling, advanced chiplet test, and open automation standards, with the goal of linking fabrication, assembly, and test into a single decision chain.

Soitec’s René Jonker argues the wafer is becoming a central AI design lever

At SEMICON West 2026, Soitec’s Chief Product Officer René Jonker described how engineered substrates are moving closer to the center of AI system design. He pointed to RF-SOI, FD-SOI, Power-SOI, POI and Photonics-SOI as examples of how material properties can be built into the starting wafer before transistor fabrication begins, and said the shift toward optical links and heterogeneous materials is expanding that role.

SK Hynix posts record Q3 as AI memory demand lifts prices and margins

SK Hynix delivered its first quarter above 100 trillion won in revenue, with operating profit rising to a record 83.33 trillion won and operating margin reaching 80%. The results were driven by sharply higher DRAM prices, easing HBM4 supply concerns, and long-term capacity agreements that point to a tighter memory market through 2030.

AI chip growth is reshaping materials, equipment, and packaging

Rising AI performance targets are putting semiconductor manufacturing materials, process equipment, and advanced packaging under new pressure. The focus is shifting from chip design alone to the entire production chain, where tighter tolerances, stronger thermal demands, and more complex multi-die packages now determine whether advanced designs can be built reliably at scale.

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October 29, 2026 Design & EDA

Physics-based validation is becoming the benchmark for trustworthy agentic EDA

Semiconductor design agents are only reliable when every autonomous step is checked against deterministic physics-based EDA engines. Siemens describes a multi-stage electro-thermal 3D-IC workflow in which validation happens continuously, not only at the end of a run.

Why AI data centers are turning to silicon photonics and CPO

AI systems can still stall even with tens of thousands of GPUs when data movement becomes the bottleneck. Silicon photonics and co-packaged optics (CPO) are emerging as ways to move more of that traffic from electrical links to light, reducing loss, power consumption, and heat in large-scale AI networks.

Vinci raises $250 million to speed physics analysis in hardware design

Vinci says it has closed a $250 million Series B at a $1.5 billion valuation and is expanding its physics analysis platform for semiconductor engineering. The company wants to make thermal, thermo-mechanical and convective fluid analysis available while designs are still changing, so engineers can assess placement, power and packaging choices before decisions become costly to reverse.

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October 29, 2026 Research

Shift Left in Chip Design Is Becoming More Iterative and Less Linear

AI agents and digital twins are pushing design decisions earlier in the chip flow, but verification, trust in surrogate models, and multi-physics complexity remain major limits. Several experts argue that the next phase of shift left will be less about freezing specifications early and more about refining architectures and implementation choices as new information appears.

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October 29, 2026 Companies & Market

Infineon links edge AI, SDVs and data-center power to the 800 VDC transition

At its OktoberTech event, Infineon tied together three shifts in semiconductor demand: more AI processing at the edge, a slower but ongoing move toward software-defined vehicles, and the push from 800 VDC sidecars toward future 1 MW rack power architectures. The company also pointed to its Dresden fab as new manufacturing capacity for power and analog/mixed-signal devices.

AI-native root cause analysis aims to cut the cost of regression triage

As semiconductor designs grow larger and regressions produce more simultaneous failures, debugging is turning into an orchestration problem. An AI-native workflow combines intelligent binning, witness simulation reruns, autonomous root cause analysis, and verification to reduce the number of failures that need separate investigation and to spend compute only where it is most useful.