Short updates from the semiconductor industry, with context and links to the relevant chapters. RSS
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October 15, 2026 Companies & Market
Infineon has signed a supply agreement with Wolfspeed for 200 mm silicon carbide wafers, adding another step to its effort to strengthen supply chain resilience for SiC-based power devices. The agreement centers on wafer supply rather than finished components and points to continued scaling in the silicon carbide value chain.
October 15, 2026 Research
As designs move into sub-5nm nodes, vias have become a major weak point in the interconnect stack. Automated, signoff-aware via insertion shifts optimization into implementation, adding redundant vias to reduce resistance, improve IR drop behavior, and strengthen electromigration margins while avoiding late-stage ECO loops.
October 16, 2026 Research
Langdao Silex (Shanghai) Technology has publicly presented an extreme ultraviolet light source prototype rated at 15 W and described as 90% localized. The debut marks a step in domestic lithography development in China, but the system is still reported to be three to five years away from mass production, with output power and long-term stability remaining the main engineering hurdles.
October 16, 2026 Supply Chain & Sites
TSMC and GlobalFoundries are drawing attention to a fast-expanding market in which mature wafer processes support advanced packaging rather than leading-edge logic. Silicon interposers, through-silicon vias, and embedded deep trench capacitors are emerging as the main demand drivers for this capacity, creating a sizable opportunity around older process nodes.
October 16, 2026 Companies & Market
TSMC said demand for CPUs tied to agentic AI continues to rise even as overall AI demand remains very strong. The company also pointed to advanced packaging and silicon interposer capacity as critical constraints, while higher costs from new fabs and N2 ramp-up continue to weigh on margins.
October 16, 2026 Industry & People
A dense week in semiconductors brought fresh fab expansion, new packaging and test initiatives, stronger AI-related spending signals, and continued momentum in China’s memory and EUV efforts. TSMC and ASML both reported strong quarters, while startups in photonics and 3D compute secured new funding and quantum hardware teams posted notable technical progress.
October 16, 2026 Companies & Market
Patent filings analyzed by SemiAnalysis suggest that ASML is preparing a die-to-wafer hybrid bonder, signalling a second step beyond lithography into advanced packaging. The tool would place ASML in direct competition with Besi and with other front-end equipment makers that are targeting the same packaging market as transistor scaling becomes more difficult and expensive.
October 16, 2026 Industry & People
At iTechCon 2026, industry and research speakers argued that AI value is shifting from standalone chips toward co-design across hardware, models, software, packaging, and system architecture. The discussion highlighted Taiwan’s strengths in semiconductor manufacturing and advanced packaging, but also its need to deepen software capability, cross-disciplinary talent, and startup support as AI moves into inference, agentic AI, edge devices, and physical AI.
October 16, 2026 Industry & People
SEMICON West 2026 in San Francisco framed semiconductors as a trillion-dollar industry and put AI at the center of the next fab buildout. The show highlighted new inspection tools from ZEISS, panel-level packaging deposition from Von Ardenne, motion-control equipment from Heidenhain, materials work from Mitsubishi Chemical Group, and workforce programs led by ABM.
October 18, 2026 Research
Maskless EUV lithography could offer a middle ground between serial electron-beam writing and conventional masked EUV. Instead of relying on a custom photomask, a programmable optical element would project digital patterns directly onto the wafer, with the aim of reducing mask cost and shortening design iteration cycles for low-volume and rapidly changing chip designs.
October 19, 2026 Research
Researchers from UC Berkeley, Samsung Electronics, and Intel have reported a nanoelectromechanically gated gain-cell eDRAM design that addresses three long-standing drawbacks of gain-cell memory: limited retention, parasitic coupling, and boosted write-voltage requirements. The approach targets the density and energy-efficiency advantages of gain cells while trying to remove the mechanisms that have kept embedded DRAM from scaling more cleanly.
October 19, 2026 Design & EDA
Calibre DesignEnhancer Via automates the insertion of additional vias to improve resistance, electromigration margin and routing density in physical design. The flow also avoids short-prone regions, aiming to keep layouts DRC-clean while reducing late signoff iteration.
October 19, 2026 Research
Embedded memory has become the main limiter in AI and HPC SoCs, taking more than half of total die area while constraining bandwidth, latency, and energy efficiency. Synopsys is addressing that shift with memory IP tuned for RibbonFET and PowerVia, backed by SRAM and Register File silicon results on Intel 18A that show 5% to 10% density gains and up to about 4% ISO-power performance improvement.
October 20, 2026 Industry & People
Artificial intelligence is shifting the semiconductor bottleneck from individual devices to the full computing system. Applied Materials says future progress will depend on tighter coordination across processors, memory, interconnects, advanced packaging, power efficiency and thermal management, with earlier collaboration needed to avoid late-stage integration problems.
October 20, 2026 Artificial intelligence
A fab does not hand out recipe changes on trust, and that same logic can be extended to autonomous agents. The article argues that agentic AI should earn decision authority through qualification, management of change, and statistical control, with autonomy granted only in narrow decision classes and revoked automatically when behavior drifts outside limits.