Short updates from the semiconductor industry, with context and links to the relevant chapters. RSS
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September 28, 2026 Manufacturing & Processes
Advanced substrates are moving away from interchangeable standard parts as larger packages, finer routing, and embedded functions tighten the link between material set, layout, and process window. Capacity still matters, but it no longer solves the full manufacturing problem by itself.
September 28, 2026 Companies & Market
At TSMC’s OIP Conference in Santa Clara, SK hynix showcased HBM4, HBM4E, server DRAM, SSDs and a chiplet-based SSD controller strategy for future PCIe generations, while also receiving TSMC’s Partner of the Year Award for the second year in a row.
September 27, 2026 Companies & Market
The Singapore-based company is positioning its chip lineup for industrial automation, AI data centers, and digital energy applications. At the center are N32 microcontrollers with Cortex-M4F or Cortex-M7 cores, integrated fieldbus and interface connectivity, and TPM 2.0-based security chips.
September 26, 2026 Research
Researchers from TU Munich, the University of Modena and Reggio Emilia, and Applied Materials have published a system-technology co-evaluation flow that compares A7 CFET and A10 NSFET technologies from parasitic RC effects to chip-level reliability.
September 25, 2026 Companies & Market
A SemiWiki analysis of TSMC’s AI-era roadmap highlights how the company is tightening the link between process technology, EDA, and IP through its Design & Technology Platform under LC Lu. The piece also points back to TSMC’s earlier PDK work and its role as a precursor to OIP.
September 25, 2026 Industry & People
TSMC’s North America OIP ecosystem forum brought a new round of partnership announcements, while research moved ahead in photonics, quantum processors and test methods. At the same time, AI design flows, materials shortages and workforce training remained central topics across the industry.
September 24, 2026 Design & EDA
AI is moving deeper into EDA, but the article argues that speed alone is not enough. Trust in automated design flows will depend on formal proof, semantic continuity across tools, and auditable handoffs that preserve design intent from one stage to the next.
September 24, 2026 Research
Arteris is advocating a multi-die NoC architecture in which native packet traffic crosses the die boundary directly, without cache-line translation or AXI tunneling. The company argues that an invariant interface is a better fit for heterogeneous chiplets in data-heavy physical AI systems.
September 24, 2026 Design & EDA
Multi-chiplet heterogeneous integration is pushing design data, IP traceability, and revision control into the critical path. Semiconductor Engineering argues that without a single source of truth, wrong versions, missed ECOs, and overwrites can quickly turn into delays or even product failure.
September 23, 2026 Companies & Market
Cadence has expanded its ChipStack AI Super Agent platform with a new RTL generation agent that turns natural-language specifications into RTL while aligning analysis, verification, and refinement to PPA targets. Early evaluations show lower area and power versus pure foundation-model code generation, with functional accuracy reported at 100%.
September 23, 2026 Companies & Market
IC-Link by imec has joined the TSMC OIP Cloud Alliance, expanding its collaboration with TSMC to provide secure cloud access to advanced-node technology, PDKs, and mixed-partner EDA flows for ASIC and silicon photonics development.
September 22, 2026 Devices & Products
Space-qualified analog ICs are no longer limited to expensive, order-to-build programs. Vendors are increasingly listing basic analog functions such as current sensing, buffering, and temperature measurement as standard catalog items, reducing schedule risk and cost for satellite designers.
September 22, 2026 Devices & Products
Infineon’s PSoC Control C3 Performance Line combines dual-core Arm Cortex-M33 operation at up to 200 MHz with a programmable power control accelerator, WBG readiness, and post-quantum cryptography for secure firmware handling in demanding power and motor applications.
September 22, 2026 Manufacturing & Processes
As AI accelerators and HPC processors scale to more cores, chiplets, and scan elements, Synopsys is pairing unified test compression with a programmable streaming fabric to move test data more efficiently across large hierarchical designs.
September 22, 2026 Research
A technical paper from the University of Minnesota outlines design methods for delivering very high power in advanced 3D heterogeneous integration, where pin-count limits and power density make robust supply delivery increasingly difficult.