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October 22, 2026 Manufacturing & Processes

Stacked-die architectures push power delivery into the spotlight

Multi-chip and stacked-die designs are becoming a main route for continued scaling in AI and HPC, but they also raise current density, multiply voltage domains, and tighten power-delivery constraints inside the package. Intel Foundry is advancing integrated voltage-regulation options, including FIVR, CoaxMIL magnetic inductors, and the capacitor-based C2VR approach, to move conversion closer to the load and improve power integrity.

Self-aligned CFET concept targets CMOS scaling beyond 10 Å

A proposed self-aligned complementary FET architecture stacks NMOS and PMOS devices vertically to push density past the limits of conventional GAA nanosheets. Digital twin simulation shows a 6T SRAM bit cell of 0.0094 µm², a 52.7% area reduction versus N3, and at least a 10 nm overlay window on critical contact layers.

Computational Lithography Moves Beyond EPE as a System-Level Problem

At SPIE Photomask Technology + Extreme Ultraviolet Lithography, an expert panel argued that edge placement error is no longer just a lithography metric. The discussion tied EPE to mask structure, scanner behavior, resist variability, etch, metrology, OPC, and downstream integration, and called for richer measurements, explainable AI, and cross-domain workflows to improve manufacturability and yield.

India’s OSAT expansion pushes semiconductor test capacity and flexibility to the foreground

As five semiconductor plants in India enter commercial production, OSATs are under pressure to secure enough test capacity for a wider mix of devices. NI says Kaynes Semicon has chosen its Semiconductor Test System, while other Indian OSATs are still qualifying equipment and evaluating test architectures for both legacy parts and new designs.

Synaptics pushes edge-AI MCUs toward multimodal workloads with tiered memory

Synaptics has introduced the Astra SR200 series, an MCU family that combines Arm Cortex-M85 and Cortex-M52 cores with up to 400 GOPS of AI acceleration, 256 MB of custom DRAM and hardware security. The company positions the devices as an xMCU class aimed at running larger edge-AI models and multimodal workloads directly on the device.

Infineon joins Microsoft, NVIDIA and UnternehmerTUM in Physical AI Growth Lab for startups

Infineon, Microsoft, NVIDIA and UnternehmerTUM Accelerator have launched the Physical AI Growth Lab, an equity-free program for European physical AI, robotics and industrial AI startups. The initiative combines hardware access, cloud and AI infrastructure, mentoring and investor links to help selected teams move from prototype to commercial scale.

New benchmark pushes chip-design AI beyond functional correctness

ChipAgents and NVIDIA have introduced Build-A-Chip-Bench, an end-to-end benchmark for AI agents that stretches from specification to verified GDS in digital IC design. The setup tests not only RTL correctness, but also whether an agent can preserve behavior while meeting timing, area, power, and routing constraints across synthesis and physical implementation.

CPO Test Scaling Runs Into Fiber Alignment, Connector Wear, and RF Probing Limits

High-volume testing for co-packaged optics is being pushed beyond single-die operation, but fiber alignment remains the main bottleneck. At the same time, connector durability, warpage, and the need to combine optical and electrical measurements are making production test architectures more complex.

October 20, 2026 Devices & Products

Automotive Sensor Supply Eliminates Switching Pre-Regulator by Gating the LDO

A discrete automotive sensor supply design removes the usual DC-DC pre-regulator and instead keeps the linear pass stage off for most of the time. A CPU pin both monitors the output and disables the supply, while a transistor-based short-circuit trip and automotive battery protection remain in place.

Singapore Builds a Technology-Translation Path from Chip Research to Manufacturing

Singapore is tying together chip research, startups, and manufacturing with platforms for SiC power devices, metalenses, and silicon photonics. A*STAR, MetaOptics, Advanced Micro Foundry, and GlobalFoundries illustrate how deep-tech work can move from laboratory development into industrial-scale production.

ASML and Xanadu Focus on Lithography-Driven Photon Loss in Photonic Quantum Hardware

ASML and Xanadu are examining whether tighter lithographic control can reduce photon loss in photonic quantum processors. The work ties optical loss to line-edge roughness, sidewall profile, process variability and pattern-transfer effects, with the goal of improving the prospects for fault-tolerant photonic hardware.

How fabs can govern autonomous agents through recipe authority and process control

A fab does not hand out recipe changes on trust, and that same logic can be extended to autonomous agents. The article argues that agentic AI should earn decision authority through qualification, management of change, and statistical control, with autonomy granted only in narrow decision classes and revoked automatically when behavior drifts outside limits.

AI is pushing semiconductor innovation beyond the chip

Artificial intelligence is shifting the semiconductor bottleneck from individual devices to the full computing system. Applied Materials says future progress will depend on tighter coordination across processors, memory, interconnects, advanced packaging, power efficiency and thermal management, with earlier collaboration needed to avoid late-stage integration problems.

Embedded memory IP targets the new bottleneck in AI and HPC SoCs

Embedded memory has become the main limiter in AI and HPC SoCs, taking more than half of total die area while constraining bandwidth, latency, and energy efficiency. Synopsys is addressing that shift with memory IP tuned for RibbonFET and PowerVia, backed by SRAM and Register File silicon results on Intel 18A that show 5% to 10% density gains and up to about 4% ISO-power performance improvement.

Calibre-Aware Via Insertion Targets Short-Resilient Physical Design

Calibre DesignEnhancer Via automates the insertion of additional vias to improve resistance, electromigration margin and routing density in physical design. The flow also avoids short-prone regions, aiming to keep layouts DRC-clean while reducing late signoff iteration.